The present invention relates to a novel method for making bottle-shaped deep trench for use as storage node in sub-micron-sized semiconductor devices. More specifically, the present invention relates to an improved method for fabricating storage nodes into a sub-micron-sized semiconductor substrate, the storage node having the form of a bottle-shaped deep trench with an enlarged diameter, or more generally speaking, with enlarged circumference or cross-sectional area in the bottom portion thereof. The method disclosed in the present invention greatly simplifies the manufacturing procedure by eliminating and replacing many of the complicated steps required in the conventional processes, while allowing the storage capacity of the deep trench capacitor to remain the same or even be increased. The present invention also relates to the improved sub-micron semiconductor deep-trench storage node made from the novel process, and the semiconductors incorporating the same.
A capacitor comprises a dielectric layer sandwiched by a pair of spaced conducting plates. There are two basic types of capacitors provided in a semiconductor device, for example, dynamic random access memory (DRAM): the crown-type capacitors and the deep-trench type capacitors. As the trend in the fabrication of semiconductor devices is toward ever-increasing density of circuit components that can be tightly packed per unit area, there are great demands to develop technologies that can reduce the surface area to be taken by individual circuit components. As a result, deep trench technologies have been developed which result in structures, particularly large area capacitors, that are vertically oriented with respect to the plane of the substrate surface.
A deep trench capacitor typically comprises a dielectric layer formed on the sidewalls of a deep trench, which is formed into and surrounded by a highly doped buried plate (which constitutes the first conducting plate), and a highly doped poly fill (which constitutes the second conducting plate), which fills the deep trench. The dielectric layer separates the first and the second conducting plates. The capacitance of the deep trench capacitor is determined by the total sidewall surface of the trench, which, in turn, is determined by the diameter, or more specifically the circumference, of the deep trench. As the semiconductor fabricating technology moves into the sub-micron or even deep sub-micron range, it is increasingly recognized that the present technology for making deep trench capacitors may be inadequate. For deep sub-micron semiconductor devices, a deep trench can have a length-to-width aspect ratio of 35:1 or even greater. With current technology, the diameter (or width or circumference) of the trench generally decreases with depth. Such a tapered cross-sectional area causes a significant decrease in the overall sidewall surface of the trench, and, consequently, the capacitance provided by the deep trench capacitor. This problem is expected to become even more profound as we move into the next generation of ULSI fabrication technologies that are characterized with critical dimensions of 0.15-micron or even finer.
Several techniques have been developed for fabricating the so-called bottle-shaped deep trench capacitors. All these techniques are relatively complicated and involve repeated applications of chemical vapor deposition, controlled etching, etc., as well as the need for using photoresists. FIG. 1 shows a typical bottle-shaped deep trench capacitor fabricated using the prior art process.
FIG. 1 shows that a conventional bottle-shaped deep trench 106 includes an enlarged bottom portion 112a, which is filled with a first conducting material. The bottle-shaped deep trench 106 is formed into a semiconductive substrate 100. A diffused zone 118 serves a first conducting plate. The diffused zone 118 is separated from the first conducting material in the bottom portion by a pad oxide layer 120a. FIG. 1 also shows another pad oxide layer 102 and a hard mask layer 104, both of which are required in forming the deep trench.
As discussed above, the conventional processes involve repeated applications of chemical vapor deposition, recessing, and etching, and the resultant bottle-shaped deep trench capacitor typically contains a second conducting plate which is made of three conducting layers (which can also be appropriately called xe2x80x9csectionsxe2x80x9d, since they are stacked above one another). All these three layers can be made of the same material and may look as if the second conducting plate contains only an integrated layer. However, it is important to note that, due to the process steps involved, the second conducting plate typically contains conducting layers that are formed in three separate stages. The second conducting layer 126 is formed after the formation of the first conducting layer 112a, and a collar oxide 124. The third conducting layer 128, which is in contact with the semiconductive substrate 100, is formed after the removal of part of the collar oxide 124 and the corresponding part of the second conducting layer 126. Thus, with the conducting layers alone, the conventional processes involve at least three cycles of deposition and controlled etching. It may be possible to reduce the number of deposition/etching cycles involved in the formation of the conductive layers, but this may result in other process complexities.
In order to meet consumers"" demand and expectation of continual lowered price of electronic components, it is necessary to find ways that can significantly simplify the semiconductor fabrication process so as to reduce the manufacturing cost. This is particularly important for the fabrication of some of the most common devices such as DRAM. It is equally important to develop processes that will also improve the integrity of the resultant products, so as to reduce the failure rate and further lower the fabrication cost.
The primary object of the present invention is to develop an improved process for the manufacturing of bottle-shaped deep trench capacitors which will reduce the fabrication cost while maintaining or even improving product performance and yield rate. More specifically, the primary object of the present invention is to develop an improved process which minimizes the number of deposition/controlled etching cycles required for the manufacturing of bottle-shaped deep trench capacitors without adversely affecting the performance of the resultant product. In fact, the modifications made in the process of the present invention actually improve the integrity of the bottle-shaped deep trench capacitor, resulting in not only cost savings but also increased product yield.
The process disclosed in the present invention for the fabrication of bottle-shaped deep trench capacitors includes the following main steps:
(1) Forming a pad oxide layer and a hard mask layer on the surface of a semiconductive substrate;
(2) Using a photolithography process to form a vertically elongated trench (i.e., deep trench) through the oxide and hard mask layers and into the substrate;
(3) Partially filling the deep trench with a first dielectric material to form a first dielectric layer having a first predetermined depth intended for the deep trench capacitor;
(4) Forming a sidewall spacer in the deep trench above the dielectric layer, the sidewall spacer being made from a second dielectric material having a different etchability from the first dielectric material as well as allowing low diffusion rate for ions;
(5) Removing the first dielectric layer;
(6) Using the sidewall spacer as a mask, causing the exposed portion (i.e., the bottom portion below the first predetermined depth) of the substrate in the deep trench to be oxidized, then removing the oxidized substrate;
(7) Forming an ion-doped conformal layer around the side walls of the deep trench, including the sidewall spacer and extending to the hard mask layer;
(8) Heating the substrate to cause doping ions to diffuse into the substrate in the deep trench not covered by the sidewall spacer, the diffused region becomes the first conductive plate;
(9) Removing the entire ion-doped conformal layer;
(10) Forming a conformal second dielectric layer covering the surface of the deep trench including the sidewall spacer, then filling the deep trench with a first conductive material to a second predetermined depth which is above the first predetermined depth;
(11) Removing the sidewall spacer and the second dielectric layer above the second predetermined depth; and
(12) Filling the deep trench with a second conductive material.
With the process of the present invention, because the ion-doped layer is formed on the sidewall spacer, there is no need to remove the upper portion of the ion-doped layer prior to performing the diffusion step, which is required in the prior art processes. The steps of filling the first and second conductive materials involve filling the deep trench with an appropriate conductive material then etching the conductive material to respectively desired depths. Because the neck portion of the deep trench is already protected by the sidewall spacer, there is no need to form an oxide collar in the present invention. Furthermore, because the upper-most conductive layer must be in contact with the semiconductive substrate, and because the oxide collar is formed after the formation of the first conducting layer, the prior art processes required the step of forming an intermediate conductive layer which is defined by the oxide collar and is not in contact with the substrate, then removing the upper portion of the oxide collar. The present invention eliminates the need for such intermediate step. The presence of the nitride layer between the first and second predetermined depths further improves the insulation between the first and second conductive plates, and thus improving the integrity of the final product.